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? 2001 fairchild semiconductor corporation ds500391 www.fairchildsemi.com january 2001 revised august 2001 fstud16450 configurable 4-bit to 20-bit bus switch with -2v undershoot protection and selectable level shifting fstud16450 configurable 4-bit to 20-bit bus switch with -2v undershoot protection and selectable level shifting general description the fairchild universal bus switch fstud16450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed cmos ttl-compatible bus switching. the low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. the fstud16450 is designed to allow ?customer? configu- ration control of the enable connections. the device is organized as either a 4-bit, 5-bit, 10-bit or 20-bit bus switch. 8-bit and 16-bit configurations are also achievable (see functional description). the device's bit configuration is chosen through select pin logic. (see truth table). when oe x is low, port a x is connected to port b x . when oe x is high, the switch is open. the a and b ports are ?undershoot hardened? with uhc ? protection to support an extended range to 2.0v below ground. fairchild's integrated ?undershoot hardened circuit? (uhc) senses undershoot at the i/o's, and responds by preventing voltage differentials from develop- ing and turning on the switch. another key device feature is the addition of a level shifting select pin, ?s 2 ?. when s 2 is low, the device behaves as a standard n-mos switch. when s 2 is high, a diode to v cc is integrated into the circuit allowing for level shifting between 5v inputs and 3.3v outputs. features undershoot hardened to ? 2v (a and b ports) voltage level shifting 4 ? switch connection between two ports minimal propagation delay through the switch low l cc zero bounce in flow-through mode control inputs compatible with ttl level see applications note an-5008 for details also packaged in plastic fine-pitch ball grid array (fbga) (preliminary) applications note select pins s 0 , s 1 , s 2 are intended to be used as static user configurable control pins. the ac performance of these pins has not been characterized or tested. switching of these select pins during system operation may tempo- rarily disrupt output logic states and/or enable pin controls. ordering code: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. note 1: bga package available in tape and reel only. uhc ? is a trademark of fairchild semiconductor corporation. order number package number package description fstud16450gx (note 1) bga54a (preliminary) 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide [tape and reel] fstud16450mtd mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 fstud16450 connection diagrams pin assignment for tssop pin assignment for fbga (top thru view) pin descriptions fbga pin assignments pin name description oe 1 , oe 2 bus switch enables 1a, 2a bus a 1b, 2b bus b s 0 , s 1 bit configuration enables s 2 level shifting diode enable nc no connect 123456 a 1a 3 1a 2 oe 1 oe 2 1b 2 1b 3 b 1a 5 1a 4 1a 1 1b 1 1b 4 1b 5 c 1a 7 1a 6 gnd oe 5 1b 6 1b 7 d 1a 9 1a 8 gnd v cc 1b 8 1b 9 e 2a 1 1a 10 s 0 v cc 1b 10 2b 1 f 2a 3 2a 2 s 1 s 2 2b 2 2b 3 g 2a 5 2a 4 v cc gnd 2b 4 2b 5 h 2a 7 2a 6 2a 10 2b 10 2b 6 2b 7 j 2a 9 2a 8 oe 4oe 3 2b 8 2b 9
3 www.fairchildsemi.com fstud16450 logic diagrams 20-bit configuration (configuration 1) 5-bit configuration (configuration 3) 10-bit configuration (configuration 2) 4-bit configuration (configuration 4)
www.fairchildsemi.com 4 fstud16450 functional description the device can also be configured as an 8 and 16-bit device by grounding the unused pins in configurations 2 and 1 respectively. the 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and tying the remaining enable pin (oe ) high. truth tables (x = v cc or gnd) (see functional description) select pin s 2 mode l std. nmos switch h level shifting diode enabled configuration 1 s 0 = s 1 = l 20-bit configuration inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 lxxxx 1a 1-10 = 1b 1-10 , 2a 1-10 = 2b 1-10 hxxxx z configuration 2 s 0 = l, s 1 = h 10-bit configuration inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 1a 1-10 = 1b 1-10 2a 1-10 = 2b 1-10 lxxlx 1a x = 1b x 2a x = 2b x lxxhx 1a x = 1b x z hxxlx z 2a x = 2b x hxxhx z z configuration 3 s 0 = h, s 1 = l 5-bit configuration inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 1a 1-5 , 1b 1-5 1a 6-10 , 1b 6-10 2a 1-5 , 2b 1-5 2a 6-10 , 2b 6-10 llllx1a x = 1b x 1a y = 1b y 2a x = 2b x 2a y = 2b y lllhx1a x = 1b x 1a y = 1b y 2a x = 2b x z llhlx1a x = 1b x 1a y = 1b y z2a y = 2b y llhhx1a x = 1b x 1a y = 1b y zz lhllx1a x = 1b x z2a x = 2b x 2a y = 2b y lhlhx1a x = 1b x z2a x = 2b x z lhhlx1a x = 1b x zz2a y = 2b y lhhhx1a x = 1b x zzz hlllx z 1a y = 1b y 2a x = 2b x 2a y = 2b y hllhx z 1a y = 1b y 2a x = 2b x z hlhlx z 1a y = 1b y z2a y = 2b y hlhhx z 1a y = 1b y zz hhl l x z z 2a x = 2b x 2a y = 2b y hhlhx z z 2a x = 2b x z hhhl x z z z 2a y = 2b y hhhhx z z z z
5 www.fairchildsemi.com fstud16450 truth tables (continued) configuration 4 s 0 = s 1 = h 4-bit configuration inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 1a 1-4 , 1b 1-4 1a 5-8 , 1b 5-8 2a 3-6 , 2b 3-6 2a 7-10 , 2b 7-10 1a 9-10 , 2b 9-10 2a 1-2 , 2b 1-2 lllll1a x = 1b x 1a y = 1b y 2a x = 2b x 2a y = 2b y 1a z = 1b z 2a z = 2b z llllh1a x = 1b x 1a y = 1b y 2a x = 2b x 2a y = 2b y z lllhl1a x = 1b x 1a y = 1b y 2a x = 2b x z 1a z = 1b z 2a z = 2b z lllhh1a x = 1b x 1a y = 1b y 2a x = 2b x zz llhll1a x = 1b x 1a y = 1b y z2a y = 2b y 1a z = 1b z 2a z = 2b z llhlh1a x = 1b x 1a y = 1b y z2a y = 2b y z llhhl1a x = 1b x 1a y = 1b y zz 1a z = 1b z 2a z = 2b z llhhh1a x = 1b x 1a y = 1b y zzz lhlll1a x = 1b x z2a x = 2b x 2a y = 2b y 1a z = 1b z 2a z = 2b z lhllh1a x = 1b x z2a x = 2b x 2a y = 2b y z lhlhl1a x = 1b x z2a x = 2b x z 1a z = 1b z 2a z = 2b z lhlhh1a x = 1b x z2a x = 2b x zz lhhll1a x = 1b x zz2a y = 2b y 1a z = 1b z 2a z = 2b z lhhlh1a x = 1b x zz2a y = 2b y z lhhhl1a x = 1b x zzz 1a z = 1b z 2a z = 2b z lhhhh1a x = 1b x zzzz hllll z 1a y = 1b y 2a x = 2b x 2a y = 2b y 1a z = 1b z 2a z = 2b z hlllh z 1a y = 1b y 2a x = 2b x 2a y = 2b y z hllhl z 1a y = 1b y 2a x = 2b x z 1a z = 1b z 2a z = 2b z hllhh z 1a y = 1b y 2a x = 2b x zz hlhll z 1a y = 1b y z2a y = 2b y 1a z = 1b z 2a z = 2b z hlhlh z 1a y = 1b y z2a y = 2b y z hlhhl z 1a y = 1b y zz 1a z = 1b z 2a z = 2b z hlhhh z 1a y = 1b y zzz hhl l l z z 2a x = 2b x 2a y = 2b y 1a z = 1b z 2a z = 2b z hhl lh z z 2a x = 2b x 2a y = 2b y z hhlhl z z 2a x = 2b x z 1a z = 1b z 2a z = 2b z hhlhh z z 2a x = 2b x zz hhhl l z z z 2a y = 2b y 1a z = 1b z 2a z = 2b z hhhlh z z z 2a y = 2b y z hhhhl z z z z 1a z = 1b z 2a z = 2b z hhhhh z z z z z
www.fairchildsemi.com 6 fstud16450 absolute maximum ratings (note 2) recommended operating conditions (note 5) note 2: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 3: v s is the voltage observed/applied at either the a or b ports across the switch. note 4: the input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. note 5: unused control inputs must be held high or low. they may not float. dc electrical characteristics note 6: typical values are at v cc = 5.0v and t a = + 25 c note 7: measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by t he lower of the voltages on the two (a or b) pins. supply voltage (v cc ) ? 0.5v to + 7.0v dc switch voltage (v s ) (note 3) ? 2.0v to + 7.0v dc input control pin voltage (v in ) (note 4) ? 0.5v to + 7.0v dc input diode current (l ik ) v in < 0v ? 50 ma dc output (i out ) current 128 ma dc v cc /gnd current (i cc /i gnd ) + / ? 100 ma storage temperature range (t stg ) ? 65 c to + 150 c power supply operating (v cc) 4.0v to 5.5v input voltage (v in )0v to 5.5v output voltage (v out )0v to 5.5v free air operating temperature (t a )-40 c to + 85 c symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) min typ (note 6) max v ik clamp diode voltage 4.5 ? 1.2 v i in = ? 18 ma v ih high level input voltage 4.0-5.5 2.0 v if s 2 = high 4.5v v cc 5.5v v il low level input voltage 4.0-5.5 0.8 v if s 2 = high 4.5v v cc 5.5v v oh high level output voltage 4.5-5.5 see figure 4 v s 2 = v cc i i input leakage current 5.5 1.0 a0 v in 5.5v 010 av in = 5.5v i oz off-state leakage current 5.5 1.0 a0 a, b v cc r on switch on resistance 4.5 4 7 ? v in = 0v, i in = 64 ma, s 2 = 0v or v cc (note 7) 4.5 4 7 ? v in = 0v, i in = 30 ma, s 2 = 0v or v cc 4.5 8 12 ? v in = 2.4v, i in = 15 ma, s 2 = 0v 4.0 11 20 ? v in = 2.4v, i in = 15 ma, s 2 = 0v 4.5 35 50 ? v in = 2.4v, i in = 15 ma, s 2 = v cc i cc quiescent supply current 5.5 3 as 2 = gnd, v in = v cc or gnd, i out = 0 10 as 2 = v cc , oe x = v cc , v in = v cc or gnd, i out = 0 1.5 ma s 2 = v cc , oe x = gnd, v in = v cc or gnd, i out = 0 ? i cc increase in i cc per input 5.5 2.5 ma one input at 3.4v other inputs at v cc or gnd, s 2 = 0v 4.0 ma one input at 3.4v other inputs at v cc or gnd, s 2 = v cc v iku voltage undershoot 5.5 ? 2.0 v 0.0 ma i in ? 50 ma oe x = 5.5v
7 www.fairchildsemi.com fstud16450 ac electrical characteristics note 8: this parameter is guaranteed by design but is not tested. the bus switch contributes no propagation delay other than the rc del ay of the typical on resistance of the switch and the 50pf load capacitance, when driven by an ideal voltage source (zero output impedance). ac electrical characteristics: translating diode note 9: this parameter is guaranteed by design but is not tested. this bus switch contributes no propagation delay other than the rc de lay of the typical on resistance of the switch and the 50pf load capacitance, when driven by an ideal voltage source (zero output impedance). capacitance (note 10) note 10: t a = + 25 c, f = 1 mhz, capacitance is characterized but not tested. symbol parameter t a = ? 40 c to + 85 c, units c l = 50pf, ru = rd = 500 ? conditions figure v cc = 4.5 ? 5.5v v cc = 4.0v (s 2 = 0v) number min max min max t phl , t plh propagation delay bus-to-bus (note 8) 0.25 0.25 ns v i = open figures 2, 3 t pzh , t pzl output enable time 1.5 6.5 7.0 ns v i = 7v for t pzl figures 2, 3 v i = open for t pzh t phz , t plz output disable time 1.5 6.7 7.2 ns v i = 7v for t plz figures 2, 3 v i = open for t phz t pzh , t pzl s el (s 0, 1 ) to output enable time 1.5 7.0 7.5 ns v i = 7v for t pzl figures 2, 3 v i = open for t pzh t phz , t plz s el (s 0, 1 ) to output disable time 1.5 7.5 7.7 ns v i = 7v for t plz figures 2, 3 v i = open for t phz symbol parameter t a = ? 40 c to + 85 c, units c l = 50pf, ru = rd = 500 ? conditions figure v cc = 4.5 ? 5.5v (s 2 = v cc ) number min max t phl , t plh propagation delay bus-to-bus (note 9) 0.25 ns v i = open figures 2, 3 t pzh , t pzl output enable time 1.5 10.0 ns v i = 7v for t pzl figures 2, 3 v i = open for t pzh t phz , t plz output disable time 1.5 9.0 ns v i = 7v for t plz figures 2, 3 v i = open for t phz t pzh , t pzl s el (s 0, 1 ) to output enable time 1.5 11.0 ns v i = 7v for t pzl figures 2, 3 v i = open for t pzh t phz , t plz s el (s 0, 1 ) to output disable time 1.5 10.0 ns v i = 7v for t plz figures 2, 3 v i = open for t phz symbol parameter typ max units conditions c in control pin input capacitance 4 pf v cc = 5.0v, v in = 0v c i/o input/output capacitance ? off state ? 8pfv cc , oe = 5.0v, v in = 0v
www.fairchildsemi.com 8 fstud16450 undershoot characteristic (note 11) note 11: this test is intended to characterize the device ? s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. figure 1. device test conditions transient input voltage (v in ) waveform ac loading and waveforms note: input driven by 50 ? source terminated in 50 ? note: c l includes load and stray capacitance note: input frequency = 1.0 mhz, t w = 500 ns figure 2. ac test circuit figure 3. ac waveforms symbol parameter min typ max units conditions v outu output voltage during undershoot 2.5 v oh ? 0.3 v s 2 = 0v, figure 1 tbd tbd v s 2 = v cc parameter value units v in see waveform v r 1 = r 2 100k ? v tri 11.0 v v cc 5.5 v
9 www.fairchildsemi.com fstud16450 figure 4.
www.fairchildsemi.com 10 fstud16450 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a preliminary
11 www.fairchildsemi.com fstud16450 configurable 4-bit to 20-bit bus switch with -2v undershoot protection and selectable level shifting physical dimensions inches (millimeters) unless otherwise noted (continued) 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd56 technology description the fairchild switch family derives from and embodies fairchild ? s proven switch technology used for several years in its 74lvx3l384 (fst3384) bus switch product. fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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